1. Field
The technology described herein relates to processing signals of imaging pixels.
2. Related Art
Conventional imagers typically include an array of active pixels. FIG. 1 is a circuit schematic of a conventional complementary metal oxide semiconductor (CMOS) imaging pixel 100, referred to as a 3T imaging pixel because it includes three transistors T1, T2, and T3. The imaging pixel 100 includes photodetector 102 which generates an optical current (photocurrent) in response to detecting incident radiation. The optical current is accumulated, or integrated, on integration node 104 to generate a voltage. The voltage on the integration node 104 is maintained by an effective capacitance Cint (shown in phantom), which is the effective capacitance to ground at node 104, and which includes the photodetector capacitance, the gate capacitance of transistor T2, and any stray wiring capacitance.
The voltage on integration node 104 is read out of imaging pixel 100 as the pixel output signal by turning on the transistor T3, which connects the source of transistor T2 to a column line 106. The column line 106 connects all pixels in a single column of an array containing imaging pixel 100, and terminates on a load device (not shown) in the column circuitry at the bottom (or top) of the array. To reset the voltage of integration node 104, precharge transistor T1 is turned on. To start a new integration period, precharge transistor T1 is turned off, thereby allowing optical current to integrate on integration node 104.
The voltage on column line 106, and therefore the output signal of imaging pixel 100 when transistor T3 is on, is impacted by a number of noise sources. The noise sources include the offset voltage of T2, pixel-to-pixel variations in the “reset” or “black-level” at integration node 104 due to variations in the threshold of precharge transistor T1, charge injection into integration node 104 caused by a state transition of precharge transistor T1, reset noise (also referred to as kTC noise, where k is Boltzmann's constant, T is temperature, and C is capacitance) on integration node 104, thermal noise from T2, and flicker noise (also referred to as 1/f noise) from T2. Some, yet not all, of these noise sources are relatively constant from one integration cycle to the next, but vary from pixel-to-pixel. Those noise sources which vary from pixel-to-pixel give rise to fixed pattern noise.
Correlated Double Sampling (CDS) is a technique used to eliminate some of the noise sources listed above. In conventional CDS, the output signal of a pixel is sampled twice per integration cycle. One sample captures the reset level of integration node 104 (when precharge transistor T1 is on), while one sample captures the integrated level of integration node 104, i.e., the voltage on integration node 104 at the end of the integration period. The reset level is then subtracted from the integrated level to provide a rough value of the charge accumulated on the integration node.